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| 1 hdm8515 users manual dvb/dss compliant receiver dec. 2000 priliminary
2 direct broadcast satellite (dbs) has been one of the most succ essful new product introductions in the history of consumer electronics. this product represents the first application of digital video compression for broadcast television. originally intended to provide cable quality television services to remote areas , this product is now offering a competitive replacement to cable services in many urban areas. the first operational systems employ closed proprietary signaling structures. the european broadcasting union (ebu) has developed the first open standard (dv b - s) for dbs services. the broadcasting community has embraced this standard which is now being adopted for new systems throughout the world. this widely accepted open standard is essential for dbs to achieve full market potential. the hdm8515 tm is a f ully dvb - s&dss compliant adc/qpsk demodulator/fec device which provides an mpeg - 2 stream to be processed by the conditional access and video decompression circuits. the demodulator clocked with a fixed frequency is true variable rate over the range of 1 t o 55m symbols - per - second. this product achieves the highest performance and flexibility. it minimizes the cost of external circuits, thus reducing overall system cost. 3 hy nix semiconductor co., ltd res erves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. information furnished by hy nix semiconductor co., ltd is believed to be accurate and reliable. however, no responsibility is assum ed by hy nix semiconductor co., ltd for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under any patent rights of hy nix semiconductor co., ltd. for more information contact: address: youngdong bldg. 891, daechi - dong, kangnam - gu, seoul, 135 - 738, korea tel: 82 - 2 - 3459 - 3188 fax: 82 - 2 - 3459 - 5843 e - mail: kosb@h ynix.com 4 table of contents 1. introduction to t he hdm8515 ................................ ................................ ................................ ................... 7 1.1 f eatures and b enefits ................................ ................................ ................................ ................................ .. 8 2. hardware specific ation ................................ ................................ ................................ .............................. 9 3. technical overvie w ................................ ................................ ................................ ................................ ..... 19 3.1 d ual c hannel a nalog to d igital c onverter ................................ ................................ .................. 19 3.2 v ariable r ate d emodulator ................................ ................................ ................................ .................. 21 3.3 n oise m easurement c ircuit ................................ ................................ ................................ ..................... 23 3.4 v iterbi d ecoder ................................ ................................ ................................ ................................ ............. 25 3 .5 a utonomous a cquisition ................................ ................................ ................................ .......................... 26 3.6 r eed s olomon d ecoder ................................ ................................ ................................ .............................. 28 3.7 c lock g eneration pll ................................ ................................ ................................ ................................ . 30 3.8 dbs r eceiver ................................ ................................ ................................ ................................ ................... 35 3.9 d i se q c i nterface ................................ ................................ ................................ ................................ ........... 36 4. mechanical specif ications ................................ ................................ ................................ ..................... 37 4.1 100 p in q uad f lat p ack ................................ ................................ ................................ ................................ 37 4.2 64 p in t hin q uad f lat p ack ................................ ................................ ................................ ........................ 39 4.3 r ecommended a nalog p in c onnection ................................ ................................ ............................... 41 4.4 r ecommended c lock g eneration c ircuit ................................ ................................ ........................... 41 5. signal descriptio n ................................ ................................ ................................ ................................ ....... 42 5.1 i nputs ................................ ................................ ................................ ................................ ................................ .. 42 5.2 o utputs ................................ ................................ ................................ ................................ ............................. 42 5.3 m onit or and c ontrol i nterface ................................ ................................ ................................ ........... 45 5.4 i2c m ode ................................ ................................ ................................ ................................ ............................. 46 6. register definiti ons ................................ ................................ ................................ ................................ ..... 48 6.1 w rite r egisters ................................ ................................ ................................ ................................ .............. 48 6.2 r ead r egisters ................................ ................................ ................................ ................................ ................ 61 appendix ................................ ................................ ................................ ................................ ................................ .... 66 a1. l oop f ilter p rogramming a pplication n ote ................................ ................................ ................ 67 a2. f alse l ock e scape a pplication n ote ................................ ................................ ................................ . 70 a3. p erformance with i nterference . ................................ ................................ ................................ ......... 71 a4. n yquist c riteria c onsiderations ................................ ................................ ................................ ......... 75 5 list of figures f igure 1: t op l evel b lock d iagram ................................ ................................ ................................ .................... 7 f igure 2: i nput d ata t iming d iagram ................................ ................................ ................................ ............. 10 f igure 3: i ntel 80c88a r ead t iming d iagram ................................ ................................ ............................... 11 f igure 4: i ntel 80c88a w rite t iming d iagram ................................ ................................ ............................. 12 f igure 5: i ntel 8051 r ead t iming d iagram ................................ ................................ ................................ ..... 13 f igure 6: i ntel 8051 w rite t iming d iagram ................................ ................................ ................................ ... 14 f igure 7: m otorola r ead t iming d iagram ................................ ................................ ................................ .... 15 f igure 8: m otorola w rite t iming d iagram ................................ ................................ ................................ . 16 f igure 9: o utput t iming d iagram for n or mal p arallel ................................ ................................ ....... 17 f igure 10: o utput t iming d iagram for n ormal s erial ................................ ................................ ........... 17 f igure 11: o utput t iming d iagram for r egulated p arallel ................................ ............................... 18 f igure 12: o utput t iming d iagram f or r egulated s erial ................................ ................................ ..... 18 f igure 13: adc b lock d iagram ................................ ................................ ................................ ............................ 20 f igure 14 d emodulator b lock d iagram ................................ ................................ ................................ ........ 21 f igure 15: n oise m easurement c ircuit ................................ ................................ ................................ ........... 23 f igure 16: n oise a ccumulator as a func tion of snr and t ime ................................ ............................ 24 f igure 17: v iterbi d ecoder ................................ ................................ ................................ ................................ ... 25 f igure 18: r eed s olomon d ecoder ................................ ................................ ................................ .................... 29 f igure 19: t ypical s et t op b ox d emo dulator ................................ ................................ ............................ 35 f igure 20: m echanical c onfiguration ................................ ................................ ................................ ........... 38 f igure 21: m echanical c onfiguration ................................ ................................ ................................ ........... 40 f igure 22: a nalog p in c onnection ................................ ................................ ................................ .................... 41 f igure 23 : clock generation circuit ................................ ................................ ................................ ........... 41 f igure 24: i2c w rite to the hdm8515 ................................ ................................ ................................ .............. 46 f igure 25: i2c r ead from the hdm8515 ................................ ................................ ................................ ............ 47 f igure a1: s ymbol t iming r ecovery t ransient r esponse ................................ ................................ ....... 67 f igure a2: c arrier p hase r ecovery t ransient r esponse ................................ ................................ ........ 68 f igure a3: c arrier p hase r ecovery t ransient r esponse with l ow snr ................................ .......... 69 f igure a4: a djacent c hannel i nterfer ence of 10 d b, 1.35 s pacing ................................ .................... 72 f igure a5: p erformance with int erferer at different carrier spacings ................................ ..... 73 f igure a6: p erformance with +10 d b i nterferer ................................ ................................ ...................... 74 6 list of tables t able 1: a bsolute m aximum r atings ................................ ................................ ................................ ............... 9 t able 2: dc c haracteristics ................................ ................................ ................................ ................................ . 9 t able 3: d emodulator s pecifications ................................ ................................ ................................ ........... 10 t able 4: ac c haracteristics ................................ ................................ ................................ ............................... 10 t able 5: i ntel 80c88a r ead c ycle t iming p arameters (b usmode = 1) ................................ ................ 11 t able 6: i ntel 80c88a w rite c ycle t iming p arameters (b usmode = 1) ................................ ............. 12 t able 7: i ntel 8051 r ead c ycle t iming p ar ameters (b usmode = 1) ................................ ...................... 13 t able 8: i ntel 8051 w rite c ycle t iming p arameters (b usmode = 1) ................................ ................... 14 t able 9: m otorola r ead c ycle t iming p arameters (b usmode =0) ................................ .................... 15 t able 10 : m otorola w rite c ycle t iming p arameters (b usmode =0) ................................ ................. 16 t able 11: o utput t iming ................................ ................................ ................................ ................................ ....... 17 t able 12: e xample of a cquisition t iming ................................ ................................ ................................ ..... 27 t able 13: i2c s lave a ddress ................................ ................................ ................................ ................................ .. 47 7 1. introduction to the hdm8515 the hdm8515 digital demodulator for direct broadcast satellite receivers is a single chip solution fully compliant with the european telecommunications standards institute (etsi) specification ets 300 421. this chip integrates an a/d converter, a variable rate matched filter, a variable rate qpsk demodulator with a viterbi decoder, a deinterleaver and a reed solomon decoder. the hdm8515, which is implemented in a 0.25 micron cmos, four layer meta l process, provides variable rate capability while operating with a fixed frequency sampling clock. digital samples of baseband i and q data are generated by an internal a/d converter, then provided to the demodulator at a fixed sample rate. the root rais ed cosine filter is implemented internally with fully digital techniques. similarly, the symbol timing recovery and carrier phase tracking functions are performed entirely in the digital domain. this approach provides minimum constraints on external circ uits, thus reducing overall system costs. the hdm8515 may be configured by an external processor for a specific symbol rate, and carrier frequency along with loop gain parameters. the hdm8515 provides an external agc signal which is used to control the gain of the analog signal which is applied to the down - converters. and it also provides a digital agc internally which controls the gain of the signal out of the matched filters. in addition, the hdm8515 provides fully programmable sweep circuitry to aid in initial acquisition when large frequency offsets may be present. the digital frequency translation capability of the hdm8515 permits this part to be used in frequency multiplexing applications. in this application, an entire transponder bandwidth con taining many signals is sampled at a fixed rate. the digital oscillator within the hdm8515 is programmed to the specific desired carrier frequency within that band to permit the selected signal to be passed through the baseband filter and processed by the demodulator circuits. f igure 1 : t op l evel b lock d iagram 6 6 i q v a r i a b l e r a t e q p s k d e m o d u l a t o r v i t e r b i d e c o d e r s y n c h r o n i z a t i o n a n d d e i n t e r l e a v i n g r e e d s o l o m o n d e c o d e r 8 d a t a c l o c k d a t a q p s k l o c k n o d e s y n c 4 4 s y m b o l c l o c k v i t e r b i b i t c l o c k f r a m e s y n c 8 v i t e r b i d a t a a/d converter i2c d iseqc interface interface mcu interface ber monitoring pll c/n estimator t u n e r byte sync qpsk lock ain_i ain_q wb_agc diseqc scl_i2c sda_i2c hi_ addr[5:0] hi_ data[7:0] xtal1_in data_clk data[7:0 ] qpsk_lock frame_sync reference clk agc agc_detector 8 1.1 features and benefits * fully dvb&dss compliant * dual 6bit a/d converters * continuously variable symbol rate from 1msps to 66msps (90mhz clock) * inter nal digital root raised cosine filter * less than 0.5 db implementation loss * frequency multiplexing capability * automated frequency search * internal bias cancellation * both wideband and narrowband agc * noise calibration for antenna steering * output data rate as high as 82mbps * fixed frequency sampling clock * simple interface with tuner and analog processing * microcontroller interface * eight bit parallel or i2c monitor and control interface * i2c by - pass mode * diseqc 1. 2 interface support * dual carrier loop filter par t code package HDM8515P 100pqfp 9 2. hardware specification table 1 : absolute maximum ratings rating value unit ambient temperature under bias - 10 to 70 c storage temperature - 65 to 150 c ambient humid ity under bias 85( 85 c ,500hrs ) % thermal resistance(j a) 45 c/w junction temperature 120 c voltage on any pin vss - 0.3v to v dd + 0.5v v vdd, iovdd 4.5 v package material - compound : cel - 4630sx - lead frame : copper table 2 : dc characteristics symbol parameter min. max. units test conditions i dd dynamic current - 390 ma v dd =2 .7 , freq=90mhz iovdd interface power supply voltage 3 3.6 v normal operation vdd core power supply voltage 2.3 2.7 v normal operation v adc powe r supply voltage 2.3 2.7 v normal operation v il input low voltage 0 0.3v dd v v ih input high voltage 0.7v dd v dd + 0.5 v v ol output low voltage - 0.4 v i ol = 4 ma v oh output high voltage 2.4 - v i oh = 4 ma i ih input high current - 10 10 ua v in = 3.6, v dd = 3.6 i il input low current - 10 10 ua v dd = 3.6, v in =0 c in input capacitance - 10 pf typical 5.75pf c out output capacitance - 10 pf typical 5.97pf 10 table 3: demodulator specifications parameter min. max. sampling clock frequency 1mhz 90mhz analog input full scale range 0.9 v pp 1.1 v pp symbol rate 1msps 66msps viterbi data rate - 90mbps reed solomon data rate - 82mbps implementation loss - 0.5 db symbol rate resolution clock/(2 20 ) - carrier frequency resolution clo ck/(2 20 ) - acquisition sweep range - + or - clock/2 table 4: ac characteristics symbol parameter min. max. unit t su1 input data setup before clock 6 - ns t h1 input data hold after clock 2 - ns t pw1 low pulse width of clock 8.7 - ns t pw2 high pulse width of clock 8.1 - ns clock i_in [5:0] or q_in [5:0] t pw1 t t t pw2 su1 h1 f igure 2 : i nput d ata t iming d iagram 11 table 5: intel 80c88a read cycle timing parameters (busmode = 1) symbol parameter min. max. unit t su 1 input address and /ce setup before /re inactive 35 - ns t h1 input address and /ce hold after /re inactive 5 - ns t pw1 /re low duration 200 - ns t d1 delay from /ce to dtack active - 35 ns t doz1 delay from /re inactive to dtack in tristate mode - 10 ns t doz2 delay from /re inactive to hi_data [7:0] tristate mode 10 - ns v a l i d h i _ a d d r [ 4 : 0 ] /ce /re d t a c k h i _d a t a [ 7 : 0 ] t h1 t doz1 t su1 t doz2 t pw1 t d1 z z f igure 3 : i ntel 80c88a r ead t iming d iagram note: hi_addr[4:0] is derived from the processor(80c88a) a15 - a8 bus and hi _data[7:0] is connected to the ad7 - ad0 bus. #this page is only for HDM8515P. 12 table 6: intel 80c88a write cycle timing parameters (busmode = 1) symbol parameter min. max. unit t su1 input data setup before /we inactive 20 - ns t h1 inp ut address, data and /ce hold after /we inactive 8 - ns t pw1 /we low duration 200 - ns t d1 delay from /ce to dtack active - 35 ns t doz1 delay from /we inactive to dtack in tristate mode - 15 ns v a l i d h i _ a d d r [ 4 : 0 ] /ce /we d t a c k h i _ d a t a [ 7 : 0 ] t h1 t doz1 t su1 t pw1 t d1 f igure 4 : i ntel 80c88a w rite t iming d iagram note: hi_addr[4:0] is derived from the processor(80c88a) a15 - a8 bus and hi_data[7:0] is connected to the ad7 - ad0 bus. #this page is only for HDM8515P. 13 table 7: intel 8051 read cyc le timing parameters (busmode = 1) symbol parameter min. max. unit t su1 input address setup before /ce active 5 - ns t h1 input address and /ce hold after /re inactive 5 - ns t pw1 /re active duration 400 - ns t pd1 delay from /re active to hi_data [7:0 ] valid - 40 ns t doz1 delay from /re inactive to hi_data[7:0] tristate mode 10 - ns v a l i d h i _ a d d r [ 4 : 0 ] /ce /re h i _ d a t a [ 7 : 0 ] t su1 t doz1 pd1 t pw1 t t h1 f igure 5 : i ntel 8051 r ead t iming d iagram #this page is only for HDM8515P. 14 ta ble 8: intel 8051 write cycle timing parameters (busmode = 1) symbol parameter min. max. unit t su1 input address and data setup before /we active 5 - ns t h1 input address and data hold after /we inactive 5 - ns t pw1 /we active duration 400 - ns t su 2 /ce setup to /we active 5 - ns t h2 /ce hold after /we inactive 5 - ns v a l i d h i _ a d d r [ 4 : 0 ] /ce /we h i _ d a t a [ 7 : 0 ] t su1 t pw1 t h1 v a l i d t su2 t h2 f igure 6 : i ntel 8051 w rite t iming d iagram #this page is only for HDM8515P. 15 table 9: motorola read cycle timing parameters (busmode =0) symbol parameter min. max. unit t su1 setup time of r/w with respect to /ce active 5 - ns t su2 address setup with respect to /ds active 5 - ns t d1 delay from dtack active to data valid - 30 ns t h 1 r/w hold with respect to /ds inactive 5 - ns t h2 address hold with respect to /ds inactive 5 - ns t h3 data hold with respect to /ds inactive 10 - ns hi_addr[4:0] /ce /ds r/w dtack hi_data[7:0] valid t su2 t t t t t h2 su1 h1 d1 h3 f igure 7 : m otorola r ead t imi ng d iagram note: external pull - up resistor is required on dtack. #this page is only for HDM8515P. 16 table 10: motorola write cycle timing parameters (busmode =0) symbol parameter min. max. unit t su1 data setup to /ds active 5 - ns t su2 r/ w setup to /cs and address 3 - ns t d1 /ds delay from r/w 5 - ns t d2 dtack delay from /ds active - 40 ns t d3 dtack delay from /ds inactive - 10 ns t pw1 /ds active duration 5 - ns t h1 address, /cs and r/w hold from /ds inactive 5 - ns t h2 data hold fro m /ds inactive 5 - ns hi_addr[4:0] /cs /ds r/w dtack hi_data[7:0] valid t su2 t t t t t t d1 t pw1 h1 d2 d3 su1 h2 valid f igure 8 : m otorola w rite t iming d iagram note: external pull up resistor is required on dtack. #this page is only for HDM8515P. 17 table 11: output timi ng symbol parameter min. max. unit t su output data setup before data_clk and data_stb 5 - ns t hd output data hold after data_clk and data_stb 10 - ns data_clk data_stb frame_sync data_valid data 1 2 3 4 n n-1 n-2 n-3 xx xx xx xx xx xx xx xx xx t su t hd f igure 9 : o utput t iming d iagra m for n ormal p arallel data_clk data_stb frame_sync data_valid data [0] 1 2 3 4 8n-5 8n-6 8n-7 8 n-8 xx xx t su t hd xx xx 8n-4 8n-3 8n-2 8n-1 8n f igure 10 : o utput t iming d iagram for n ormal s erial note : in case of dvb, n is 188 in case of dss, n is 144 18 1 2 3 4 n-1 n-2 n-3 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx data_clk data_stb frame_sync data_valid data t su t hd n f igure 11 : o utput t iming d i agram for r egulated p arallel 1 2 3 4 8n-5 8n-6 8n-7 8n- 4 xx xx xx xx xx xx xx xx xx data_clk data_stb frame_sync data [0] t su t hd 8n-8 xx xx 8n-3 8n-2 8n-1 8n data_valid f igure 12 : o utput t iming d iagram for r egulated s erial note : in case of dvb, n is 188 in case of dss, n is 144 19 3. technical overview 3.1 dual channel analo g to digital converter the block diagram shown below illustrates internal configuration of the dual channel adc. baseband signals, in - phase(i) and quadrature phase(q), which are generated by down converters, are applied to the dual channel adc and quanti zed to 6 - bit digital codes respectively. the adc is optimized to allow ac coupled inputs with full scale input range of 1v + or - 10%. an lsb weight is approximately 15.6 mv. the full scale input analog conversion range (vpp) is determined by the voltag es of vtop and vbot and simply equal to (vtop - vbot). the full scale range is defined as the voltage range that accommodates 63 codes of equally spaced lsbs. also the adc supplies its own reference voltages for a/d conversions. the voltages can be monitor ed by external reference pins. the vtop, vbot represent top and bottom reference voltages respectively. ref_i, ref_q represent middle reference voltages for each channel. all these 4 reference voltage pins should be by - passed to gnd via 0.1uf capacitors. t he values of internally generated voltage of vtop and vbot are 2.0v and 1.0v respectively. vpp can be adjusted by externally applying voltages to both vtop and vbot pins respectively when different conversion ranges are necessary. vtop can be adjusted as high as 2.3v and vbot can be as low as 0.5v. a larger input range can be established by taking vtop higher and vbot lower than on - chip generated voltages. to supply necessary bias voltages for ac coupled applications, ref_i and ref_q, which are midd le reference voltages for i and q channel, are connected to the analog input pins (ain_i and ain_q ) respectively through 40 kohm resistors, as shown in the block diagram. for dc coupled applications, these voltages can be used to feed back offset compens ation signals. to insure optimum performance, a low impedance analog ground plane is recommended and should be separated from other digital ground planes. the analog power supplies should be by - passed at device to analog ground through 0.1uf ceramic ca pacitors. 20 ref. voltage gen. ain_q vtop vbot di dq 6 6 clock 6-bit adc ain_i ref_i 6-bit adc ref_q f igure 13: adc b lock d iagram 21 3.2 variable rate demodulator the block diagram illustrates the overall configuration of the variable rate qpsk demodulator. baseband in - phase (i) and quadrature (q) inputs are ap plied to the demodulator at a fixed sampling rate. these digital samples are produced by a/d converters which employ ac coupling to minimize dc offset. first frequency trans. dual fir nb agc second frequency trans. i_out q_out i_in q_in carrier tracking symbol tracking lock detect qpsk lock frequency sweeper signal strength f igure 1 4 d emodulator b lock d iagram the only significant change t o this configuration over the hdm8513a is the addition of the second frequency translator. the carrier tracking block produces two outputs, one is the frequency correction which is provided to the first frequency translator. this insures that the input to the dual fir is always centered at zero frequency error, although there may be a phase error at this point. the second output of the carrier tracking function provides the phase correction to the second frequency translator. the carrier frequency error associated with these samples is removed digitally during tracking operations by a complex multiplier and a digitally controlled oscillator, sometimes called a numerically controlled oscillator (nco). during initial acquisition, coarse frequency error is removed by a combination of the digital agc within the hdm851 5 and external analog tuning circuits. a dual filter performs the root raised cosine filtering of the frequency corrected baseband samples. this filter, which implements the function of equat ion (1), is always configured to have an impulse response duration of 8 symbols regardless of the programmed symbol rate. for low symbol rates, a large number of samples are used, while for high symbol rates a relatively low number of samples are processe d for each filter output. the outputs of the daul filters are applied to a digital 22 narrowband agc which insures that the signal is optimally scaled to the viterbi decoder to an accuracy of + or - 0.5 db to insure optimum fec performance. y[k] = s h[n] x[k - n] (1) in addition to optimizing performance of the viterbi decoder, the digital narrowband agc also insures that the performance of the symbol timing and carrier tracking loops is independent of signal level variations. an analog wideband agc is also employed to insure that the analog signal applied to the a/d converters is properly scaled. both the symbol timing and carrier tracking loops are implemented digitally, which eliminates the need for external connections to analog tuning components d uring steady state operation. this causes the requirements on the analog presampling filter to be relaxed, permitting a lower cost analog front end. for systems which require a narrow band presampling filter, and have the potential for significant frequen cy error in the lnb (several mhz) the hdm851 5 provides a high resolution measure of carrier frequency to permit periodic readjustment of the front end tuner frequency to compensate for drift. the host processor periodically reads the frequency register, t hen computes appropriate correction to the tuner frequency. the nominal symbol rate and the nominal carrier frequency are programmed into the demodulator to an accuracy provided by 20 bits of resolution, and the system accuracy is equivalent to that of t he fixed frequency sampling clock. during initial acquisition, the hdm851 5 provides an automated sweep program to facilitate carrier acquisition. the host processor loads a 20 bit register which determines the initial carrier frequency. a 16 bit regist er is programmed with the number of symbol times the receiver will dwell at each frequency. if the receiver remains at the initial frequency for the programmed number of symbol times without achieving lock, the carrier frequency is incremented by the step frequency value programmed into another 16 bit register. if no lock is achieved, the receiver will continue to increment the frequency until the maximum number of search frequencies, as determined by the value in an 8 register, is achieved. when the max imum number of search frequencies is reached, the carrier frequency returns to the initial value and the entire process is repeated. once the host processor determines that lock is achieved by observing the lock flag, it then inhibits the sweep function a nd programs loop bandwidth parameters which are optimized for steady state performance. 23 3.3 noise measurement circuit when the dbs system is being installed in any place, the most difficult part of the installation is accurate pointing of the ante nna toward the satellite. inaccurate pointing results in loss of margin and greater potential for outages in adverse weather conditions. existing systems use information from the demodulator forward error correction circuits to provide a measure of anten na pointing. unfortunately, this method is useful over a range of only several db above system threshold. the hdm8515 employs a unique circuit for accurate measure of signal strength over a 20 db range of signal to noise ratio. this method, illustrated in the block diagram, makes use of the fact that the demodulator provides 8 bits of resolution for each of the quadrature output components. this high resolution provides a means of measuring the noise component with great accuracy. the eight bit in - ph ase demodulator filter output is detected by an absolute value circuit, then passed through an iir to provide a measure of average signal amplitude. each sample is then subtracted from this average amplitude to provide an instantaneous noise sample. the absolute value of these noise samples are then averaged by a second iir to provide a measure of the noise which is roughly proportional to the noise power and inversely proportional to signal to noise ratio. finally, the figure 16 illustrates the results of simulations under different noise conditions. this figure illustrates that for signal - to - noise ratio as high as 19 db, the noise measurement circuit provides a meaningful measure of signal power with worst case resolution of 1 db. a b s o l u t e v a l u e r 2 5 5 2 5 6 8 1 6 8 a b s o l u t e v a l u e r 2 5 5 2 5 6 8 1 6 8 i n p h a s e c o m p o n e n t a v e r a g e m a g n i t u d e i n s t a n t a n e o u s d e v i a t i o n a v e r a g e d e v i a t i o n 8 1 6 8 i n p h a s e c o m p o n e n t - f igure 15: n oise m easurement c ircuit 24 f igure 16: n oise a ccumulator as a func tion of snr and t ime 25 3.4 viterbi decoder the viterbi decoder accepts 4 bit soft decision samples of the in - phase (i) and quadrature (q) components o f the received signal. once qpsk lock has been achieved, the decoder searches for the correct code rate, starting with rate 3/4, then proceeding to rate 2/3, 5/6, 7/8 and finally rate 1/2. each of the possible synchronization phases at each rate is teste d as well as the two possible carrier phase ambiguity conditions. polarity reversal is corrected in the word synchronization logic. viterbi lock is achieved when the trellis traceback algorithm converges, on the average, within a prescribed number of sym bols. although the algorithm automatically tests for carrier phase ambiguity, there is no provision to automatically correct for phase reversal. phase reversal can occur if the receiver chain, consisting of an lnb and the tuner, provides an odd number o f high side frequency translation operations. a system may be required to operate with different lnbs, some of which provide phase reversal. this condition may be corrected by the host processor, which can set a bit in the down converter to correct for p hase reversal. the viterbi decoder employs the radix two algorithm. the output buffer reserializes the data which is made available, along with the viterbi data clock as external signals. these signals permit verification of the dvb specification which is referenced to the viterbi decoder output. acs array trace-back ram traceback memory controller decoder quality estimate last-in first-out buffer data out viterbi lock clock out depuncturing logic branch metric calculator change puncture phase change carrier phase i q g1 g2 4 4 64 f igure 17: v iterbi d ecoder 26 3.5 autonomous acquisition the hdm8515 provides several features to permit signal acquistion with minimal interaction with the host microcontr oller. the host microcontroller must configure the hdm8515 for a specific symbol rate, carrier frequency, carrier sweep conditions, and tracking loop bandwidth. the microcontroller also must monitor lock status to determine when acquisition is achieved. there are many provisions in the hdm8515 to enable the system designer to implement custom algorithms for specific requirements. the microcontroller first must set the lower edge of the carrier search range in the carrier frequency registers (04, 05 and 06). then the processor configures the carrier sweep step size register (09, 0a) to a value which is less than two times the carrier pull - in range. the number of symbols per dwell is defined in registers (0b,0c), and is typically set to a value of 500 to 1000. the total search range is set by the number of search frequencies as defined in register 0d. the total sweep frequency range is this number times the carrier sweep step size. the sweep process stops once qpsk carrier lock is detected. if no lo ck is detected, the sweep process continuously repeats. the qpsk demodulator may lock to any one of four different phase reference states, only one of which produces true i and q data as it was modulated at the transmitter. if the local phase reference is plus 90 degrees or minus 90 degrees with respect to the true phase, the information provided to the viterbi decoder will be unintelligible. if the viterbi decoder is unable to achieve valid lock, it will reattempt lock with a 90 degree phase shift, wit hout external intervention. in the event that the local phase is 180 degrees from the true phase, the data provided to the viterbi decoder will be inverted, but otherwise valid. the code employed by the viterbi decoder is transparent, thus the data from the viterbi decoder will be inverted if the input is inverted. this situation is corrected in the word synchronization circuit. this circuit searches for the unscrambled sync word which occurs once per frame (every 204 bytes at the viterbi output). on ce correlation with the sync word is found, the data is reformatted as a series of bytes with the beginning of each 204 byte frame identified to provide the synchronization information required for the deinterleaver and the reed solomon decoder. if the po larity of the sync word is incorrect, the data is inverted before further processing without external interaction. the hdm8515 supports five different code rates, including 1/2, 2/3, 3/4, 5/6 and 7/8. when rate 1/2 is employed, there is a one - to - one cor respondence between incoming i and q samples and g1 and g2 terms required by the viterbi decoder. the higher rates employ punctured coding techniques which periodically cause either a g1 or g2 term to be deleted. the puncturing pattern can have 6 possi ble ambiguity states for rate 2/3, 4 states for rate 3/4, 6 states for rate 5/6 and 8 states for rate 7/8. as part of the viterbi decoding acquisition process, each puncturing state of each code must be tested. total acquisition requires search of 26 dif ferent conditions. the process starts with rate 3/4 coding and proceeds sequentially to rate 2/3, 5/6, 7/8, and finally rate 1/2. in some systems, it may be possible to experience spectral inversion. this might occur when different combinations of ln bs and tuners are employed which implement different frequency translation schemes. correction of spectral inversion must be corrected with host processor interaction. if the host processor detects that qpsk lock is achieved, but viterbi lock has not occ urred within a specified time, then a bit must be set in the demodulator which reverses the spectrum. 27 the table below illustrates a typical acquisition timing. for this example, the symbol rate is one half of the clock rate. the code rate is set to 5/6, which requires 13 trial and errors before node sync is achieved. the carrier search logic requires 10 dwells at different frequencies (500 symbols per dwell) before demodulator lock is achieved. table 12: example of acquisition timing bit times sym bols clock cycles carrier search 8,333 5,000 10,000 viterbi node sync 2,652 1,591 3,182 byte sync 16,000 9,600 19,200 deinterleaver flush 19,584 11,750 23,500 reed solomon 1,632 979 1,958 total timing 48,201 26,950 57,840 the total time required for acquisition could vary widely, depending upon the carrier search range and the time required for viterbi node sync. for this example, however , the byte sync time and the time required to flush the deinterleaver dominates the total time. if a 90mhz clock were employed, the total acquisition time would be 0.642 milliseconds for this example 28 3.6 reed solomon decoder the serial outpu t from the viterbi is provided to the word sync circuits which searches for the eight bit frame sync word which occurs every 204 bytes. by detecting the polarity of the sync word, this module can correct polarity reversals in the data provided by the vite rbi decoder. byte serial data is provided to the convolutional deinterleaver, which reorders the received symbols. this process causes errors, which typically occur in bursts from the viterbi decoder, to be distributed randomly over many blocks. this d einterleaved data is then provided to the reed solomon decoder which can reduce an error rate of 2 x10 - 4 from the viterbi decoder to less than 1 in 10 - 10 . the reed solomon decoder accepts input data in blocks of 204 bytes and produces error corrected bloc ks of 188 bytes. maximum 8 bytes per a rs block can be corrected in rs decoder. reedsolomon block includes on - chip ber calculator at the output of viterbi to monitor signal quality or estimate the snr of incoming signal. the calculated value can be read by accessing two read registers via utility bus such as i2c. it represents the number of errors among 2 20 data bits. the next process is descrambling, not to be confused with the descrambling which is part of conditional access. the purpose of scrambling the transmitted data and performing the inverse in the receiver is to insure that the spectrum of the transmitted waveform is always evenly distributed without significant discrete spectral lines. without the scrambling/descrambling process, a transmitted sequence of all ones or all zeroes would result in strong spectral components and could interfere with other signals in the same satellite transponder. the final process is data regulation. viterbi data and viterbi clock occur irregularly according to t he code rate. data clock regulation makes it possible to interface with external common interface devices. to make external bus interface more flexible, interface mode such as parallel or serial can be selected by mode selection register. parameter regis ter regulate_data_clk bit 5 of 14h register mode_serial bit 0 of 18h register clk_pol bit 7 of 14h register l normal interface mode (parallel/serial) if regulate_data_clk is reset, both parallel interface and serial interface work in normal operation which is same as hdm8513a. parallel interface or serial interface can be alternated by modifying mode_serial bit (refer to figure 9 and figure 10) l regulated interface mode (parallel/serial) if regulate_data_clk is set,all interfaces are from internal fif o designed to regulate irregular interface signals. data clock cycle is a little bit faster than the average of cycle of irregular data clock, so meaningless data can be output in invalid data period. parallel interface or serial interface can be alternate d by modifying mode_serial bit (refer to figure 11 and figure 12) l clock polarity this bit is used to select the data_clk polarity either for serial or parallel transport interface. if this bit is set to zero(default value), the transport data and control signals are latched at the positive edge of data_clk. otherwise, the signals are latched at the negative edge of data_clk. 29 word sync. deinterleaver memory viterbi data viterbi clock reed solomon decoder deinterleaver control memory descrambler word clock frame clock error flag data out data clock sync. 8 8 8 8 f igure 18: r eed s olomon d ecoder 30 3.7 clock gen eration pll an integrated vco is locked to mxn times a reference frequency provided by a external clock. 1.determining output frequency fully programmable feedback and reference divider capability allows virtually any frequency to be generated, not jus t simple multiples of reference frequency. there are two status exist (1) pll disable mode : the pll is bypassed and the external clock is directly connected to the internal clock. (2) pll enable mode : the internal cloc k is connected to the generated clock of the pll. 1.1 pll disable mode pll control setting is as follows tdm (bit 7 of 0x23 register) is set to one and bypass (bit 4 of 0x23 register) is set to one. 1.2 normal frequency mode output frequency range is limited to 160mhz. pll control setting is as follows: tdm (bit 7 of 0x23 register) is set to zero, and bypass (bit 4 of 0x23 register) is set to zero. at this condition, the output frequency, f(ck), is actually determined by the following equation. f(ck) = ---------------------------------------------- f(ck) : frequency of output f(ref): frequency of reference input feedback divisor : m[13:0]+2 , (0x25 and 0x26 registers) reference divisor : n[7:0]+1 , (0x27 register) 1.3 extende d frequency mode output frequency range is limited to 320mhz. pll control setting is as follows tdm (bit 7 of 0x23 register) is set to zero, and bypass (bit 4 fo 0x23 register) is set to one. at this condition, the output frequency, f(ck), is actua lly determined by the following equation f(ck) = -------------------------------------------------------- pre divisor : 2 p[1:0]+1 , p is bit 2 and 3 of 0x23 register 2. pll control parameter setting besides of m (feedback divisor), n (ref erence divisor), p (pre divisor) , you must determine vc (vco range control vector), lfm (loop filter mode selector), icp (charge pump bias current control f(ref) x (feedback divisor) (reference divisor) f(ref) x (feedback divisor) x (pre divisor) (reference divisor) 31 vector) values appropriately. 2.1 vc value setting according to output clock frequency, determine the vc values. 32 output clock frequency vc[1:0] p[1:0] min max 00 40mhz 100mhz 01 20mhz 50mhz 10 10mhz 25mhz 00 11 5mhz 12.5mhz 00 60mhz 100mhz 01 30mhz 50mhz 10 15mhz 25mhz 01 11 7.5mhz 12.5mhz 00 80mhz 100mhz 01 4 0mhz 50mhz 10 20mhz 25mhz 10 11 10mhz 12.5mhz 00 100mhz 100mhz 01 50mhz 50mhz 10 25mhz 25mhz 11 11 12.5mhz 12.5mhz 2.2 lfm value setting according to the table, determine the lfm value lfm (reference frequency)/(reference divisor)/15 7 les s than 0.01555 0 less than 0.0258 1 less than 0.0421 2 less than 0.070 3 less than 0.114 4 less than 0.187 5 less than 0.309 6 greater than 0.309 2.3 icp value setting according to the lfm value, you determine zero value, pole value, rlf value. lfm zero value pole value rlf value 7 external filter used external filter used external filter used 0 0.008 0.03 40 1 0.013 0.050 24.1 2 0.021 0.082 40 3 0.032 0.135 24.1 4 0.060 0.221 24.1 5 0.100 0.360 14.7 6 0.160 0.600 8.9 step 1: according to the following formula, kvcop is determined 33 kvcop = ---------------- p: pre divisor 2 p 100 34 step 2: according to the following formula, kpll is determined kpll = (zero value * pole value) 1/2 s tep 3: according to the following formula, kpd is determined kpd = 1000.0 * kpll * feedback divisor / kvcop / rlf step 4: according to the following formula, temp value is determined temp value = 2.0 * 3.14 * kpd step 5: finally, according to the following formula, icp is determined icp = 16.5 ? 16.0 / 40.0 * temp value if icp value has fraction, truncate it. 35 3.8 dbs receiver the hdm8515 dvb demodulator including a dual a/d converter and the mpeg - 2 d ecoder provide the core digital processing technology for a dbs receiver conforming with the dvb standard. 8 clock d a t a m c 6 8 3 0 6 ( m c 6 8 3 4 0 ) h o s t p r o c e s s o r l - b a n d t u n e r 4 8 0 m h z d o w n - c o n v e r t e r c o a r s e t u n i n g s t e p f r e q u e n c y c o n t r o l l o w p a s s f i l t e r w b a g c 4 8 0 m h z l o o p f i l t e r s l 1 7 1 0 s e r i a l i n t e r f a c e b s f c 7 7 g v 6 8 conditional access i n t e r f a c e a g c 2 a g c 1 f i x e d f r e q u e n c y p l l c o n t r o l 3 i f i q hdm8515 mpeg-2 demultiplexer dram video audio f igure 19: t ypical s et t op b ox d emodulator a tuner accepts an l - band rf input from the antenna/lnb assembly loca ted outside the building. a host processor controls the tuner to the nominal center frequency of the target signal. baseband i and q outputs from the downconverter are applied to an a/d converter pair which is sampled at a fixed rate, 90mhz as illustrate d in this example. the tuner is required to filter the received baseband signal to a bandwidth less than half the sampling rate, but is not required to perform matched filtering. once the hdm8515 has locked to the target signal, the host processor may read the internal registers to determine the steady state frequency error. this error would be used to make period corrections to the programmed frequency of the tuner pll. the hdm8515 provides an output which can be used to control the analog agc in the tuner. this digital signal must be filtered and amplified before applying it to the agc control element. when the loop is closed, the signal applied to the a/d converters is optimally scaled. 36 3.9 diseqc interface the diseqc system is a c ommunication bus between satellite receivers and satellite peripheral equipment, using only the existing coaxial cable. 1.1 diseqc mode according to the value of diseqc_mode of 0x31 register, diseqc mode can be changed 0: 22khz tone off 1: 22khz tone on 2: burst mode - on for 12.5ms = ? 0 ? 3: burst mode - modulated 1:2 for 12.5ms = ? 1 ? 4: modulated with bytes from diseqc instruction 1.2 diseqc instruction up to eight instruction data bytes are loaded into a bank of registers(0x29 - 0x30). i2c automatic register ad dress incrementing is turn on. the number of bytes in the diseqc instruction must be defined in the diseqc_length of 0x31 register. when the diseqc instruction data bytes have been loaded, set diseqc_mode of 0x31 register. at the same time, program diseqc_length of 0x31 register. the instruction data is modulated onto 22khz signal and output from the diseqc pin. 37 4. mechanical specifications 4.1 100 pin quad flat pack 4.1.1 pin assignment 1 data_clk 26 test6 51 hi_addr5 76 dtack 2 fr ame_error 27 vdda 52 hi_addr4 77 sda_i2co 3 frame_sync 28 vssa 53 hi_addr3 78 sda_i2c 4 vdd 29 vtop 54 hi_addr2 79 scl_i2co 5 vss 30 ain_i 55 hi_addr1 80 scl_i2c 6 diseqc 31 iovdda 56 hi_a dd r0 81 vdd 5 7 sigmadelta 32 iovssa 57 vdd 82 vss 8 symbol_cl ock 33 ref_i 58 hi_data7 83 r/w(/re) 9 wb_agc 34 ref_q 59 hi_data6 84 /ce 10 qpsk_lock 35 ain_q 60 hi_data5 85 /ds(/we) 11 iovdd 36 vbot 61 hi_data4 86 vdd 12 iovss 37 test5 62 iovdd 87 vss 13 test15 38 test4 63 iovss 88 data7 14 test14 39 test3 64 h i_data3 89 data6 15 test13 40 vddp 65 hi_data2 90 data5 16 test12 41 vssp 66 hi_data1 91 lock 17 vdd 42 test2 67 hi_data0 92 data4 18 vss 43 test1 68 vdd 93 data3 19 test11 44 test0 69 vss 94 iovdd 20 test10 45 clock 70 vb_nodesync 95 iovss 21 test9 46 xtal1 _in 71 vb_clock 96 data2 22 test8 47 xtal 1 _out 72 vb_data 97 data1 23 iovdd 48 iovdd 73 vdd 98 data0 24 iovss 49 iovss 74 vss 99 data_valid 25 test7 50 reset 75 busmode 100 data_stb 38 4.1.2 package dimensions hdm8515 23.340 23.090 20.100 19.900 80 51 50 31 30 1 81 100 17.880 17.908 14.100 13.900 0.380 0.220 0.650 typ . dvb demodulator all dimensions in mm 0.500 0.250 0.7 1.950 typ. 0.230 0.130 0.950 0.650 3.350 3.000 f igure 20: m echanical c onfiguration 39 4.2 64 pin thin quad flat pack 4.2.1 pin assignment (will be changed) 1 frame_error 17 vssa 33 vdd 49 iovss 2 frame_sync 18 vdda 34 vss 50 vdd 3 lnb_sync 19 ref_i 35 i2c_add2 51 vss 4 wb_agc 20 ref_q 36 iovdd 52 data7 5 iovdd 21 ain_q 37 iovss 53 data6 6 iovss 22 vbot 38 i2c_add1 54 data5 7 test13 23 vssa 39 i2c_add0 55 lock 8 test12 24 vdd 40 vdd 56 data4 9 vdd 25 vss 41 vss 57 data3 10 vss 26 n/c 42 vb_clock 58 iovdd 11 test11 27 n/c 43 vb_data 59 data2 12 test10 28 n/c 44 busmode 60 data1 13 test9 29 xtal1 45 sda_i2c0 61 data0 14 test8 30 iovdd 46 sda_i2c 62 data_valid 15 vtop 31 iovss 47 scl_i2c0 63 data_stb 16 ain_i 32 reset 48 scl_i2c 64 data_clk 40 4.2.2 package dimensions hdm8515t 1 16 17 32 33 48 49 64 0.50 10.00 12.00 12.00 10.00 0.27 max. 0.17 min. all dimensions in mm 0.95 min. 1.00 typ. 1.05 max. 0.15 max. 0.08r min. 0 min. 0-7 0.45 min. 1.00 ref. f igure 21: m echanical c onfiguration 41 4.3 recommended analog pin connection down converter 0.1uf 0.1uf i q 1.2uh 0.1uf 47uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf vdd vdd vto vbo ref_q ref_i vss vss ain_i ain_q agnd hdm8515 electrolyte capacitor f igure 22: a nalog p in c onnection 4.4 recommended clock generation circuit 22pf 22pf 4mhz crystal to xtal1_in to xtal1_out f igure 23: clock generation circuit 42 5. signal description 5.1 inputs xtal1 xtal1 can be configured either for sampling clock inp ut or pll reference clock input . the sampling clock rate must be a minimum of 1.33 times the symbol rate of the signal to be processed and at least equal to the total bandwidth of the signal to be processed. reset a low on this signal causes the chip to be initialized. i/o registers are not cleared by this signal. this signal is asynchronous with respect to the clock. ain_i analog input signal for i channel. this should be ac coupled with analog input source via 0.1uf capacitor. ain_q analog input signal for i channel. this should be ac coupled with analog input source via a 0.1uf capacitor. 5.2 outputs vtop top reference voltage output of about 2.0v. it should be bypassed to gnd by 0.1uf capacitor. external bias voltage can be applied i f necessary. vbot bottom reference voltage output of 1.0v. it should be bypassed to gnd by a 0.1uf capacitor. external bias voltage can be applied if necessary. ref_i middle reference voltage for i channel. it should be bypassed to gnd by a 0.1uf capac itor. ref_q middle reference voltage for q channel. it should be bypassed to gnd by a 0.1uf capacitor. data [7:0] the eight bit output data is provided in parallel format to be handed to an mpeg decoder for video and audio decompression. 43 dat a_clk the data_clk is used to latch data and control signal of transport stream . the data and control signals can be programmed to be latched either at positive or negative edge of data_clk. this signal is used in conjunction with data_valid to transfer da ta from the hdm8515 . the data_clk will continue to toggle during the 16 bytes that the data_valid signal indicates that no data is available (see figure 9 and 10). data_valid when this signal is true, data is valid. this signal is not true during th e time the 16 bytes of redundancy information is transmitted for the reed solomon decoder. frame_sync this signal is true at the first byte of a block of 188/144 bytes. data_stb this signal is used to transfer data from the hdm8515 to an mpeg decoder. this signal goes from low to high when a new byte of a 188 /144byte mpeg2 data stream block is available. this signal is inactive during the time the 16 redundancy bytes are transferred. frame_error this signal goes true when the reed solomon decoder detects that an uncorrectable number of errors have occurred. the error flag in the mpeg2 output stream is also set when this flag goes high. wb_agc this one bit output provides a measure of the external analog gain required for optimizing the signal ap plied to the analog to digital converters. this signal must be filtered, then applied to the analog gain control. clock this is a buffered clock output signal which may be used to drive other devices with the same clock which drives the hdm8515. qpsk _lock this signal goes true when the qpsk demodulator has achieved phase lock. vb_nodesync this signal goes true when the viterbi decoder has achieved node synchronization. lock this signal goes true when the output data is valid and all synchronizatio n functions have been performed. symbol_clock this signal, used for test purposes, goes true for a duration of one clock cycle for each received symbol. for symbol rates equal or greater than half the clock frequency, this signal at times may remain hig h for two successive clock cycles to indicate that two symbols have occurred. vb_data the serial output of the viterbi decoder is provided on this pin. the information rate at this point is less than the rate of the input clock ( less than 60mbps if a 60 mhz clock is employed). as long as valid convolutional encoding is employed, there is no constraint that the input signal adheres to mpeg2 format. this data is tapped priod to the polarity correction circuitry, so the data at this point may be inverted. 44 vb_clock the positive edge of this signal indicates that vb_data is valid. sigmadelta this is an one bit sigma delta d/a converter which has 8 bits of resolution. this output must be filtered with an analog low pass filter off the chip. this output m ay be used for any external analog control. diseqc this is a diseqc output to control the lnb. test[15:0] the data provided on the test output signals is defined by data value of register 14 h . refer to register 14 h . 45 5.3 monitor and control interfa ce three different modes are supported for the monitor and control interface. two of the modes are 8 bit parallel interfaces, one which supports intel microcontrollers and the other intended for motorola microcontrollers. the third mode is a serial int erface conforming to the i2c standard. the i2c mode is activated by placing busmode high at the same time both /re and /we are low simultaneously. when this mode is active, the seven bit i2c slave address of the hdm8515 is configured by the seven least significant bits of the hi_data[7:0] bus. hi_data [7:0] this bi - directional data bus is used for transferring control parameters to the demodulator and for reading the status registers within the demodulator. /ce chip enable is an active low input to the demodulator which signifies that the other control signals are active. /re read enable is an active low input to the device which, when active at the same time chip enable is true, permits the device to drive the hi_data [7:0] lines. when busmode i s 0 (motorola), this pin is read / not write (see timing diagrams). /we write enable is an active low input to the device which, when true at the same time chip enable is true, causes input data on the hi_data [7:0] bus to be transferred to the register defined by the hi_addr [4:0] bus. when busmode is 0 (motorola), this pin is not data strobe (see timing diagrams). hi_addr [4:0] the address bus defines which location within the device is to be accessed during a read or write operation. busmode busm ode selects the type of microcontroller/processor used to setup the chip. when high, an intel processor/microcontroller interface is used. when low, a motorola processor interface is used. dtack data acknowledge/data ready is a tristate output signal which informs the controlling processor that a data transfer has been acknowledged by the hdm8515. scl_i2c this pin provides the clock for the i2c interface when that mode is active. sda_i2c this pin is the data for the i2c interface and requires an external pull - up resistor as per the i2c standard. sda_i2co this pin, which can be by - passed, is the data for the i2c interface. scl_i2co this pin, which can be by - passed, provides the clock for the i2c interface. 46 5.4 i2c mode the hdm8515 utilizes the subaddress technique when the i2c mode is employed. in all cases, the hdm8515 behaves as the slave device (transmitter or receiver), whilst the host behaves as the master device. the seven bit slave address of the hdm8515 is user selectable, being defined by the inputs to hi_data[6:0] when the hdm8515 is in i2c mode. further information on the i2c bus formats and protocols is contained in the philips semiconductors i2c specification. in a 100pin configuration, sda_i2co and scl_i2co are added to provide a by - passing function. when i2c bypass bit is set to zero, sda_i2co and scl_i2co are disabled. 5.4.1 i2c write to hdm8515 the master initiates communication with the hdm8515 by generating a start condition and then sen ding the hdm8515 the slave address defined by the seven bit hardwired address on hi_data [6:0]. per i2c convention, the eighth bit in the address byte is a read/not write bit, and should be set to zero. the hdm8515 will acknowledge the correctly sent sla ve address, following which the master sends an eight bit word address; this is the address of the first hdm8515 register to be written to. once the word address has been acknowledged by the hdm8515, the master can then transmit the byte to be written to the word address. once this byte is acknowledged by the hdm8515, the word address is automatically incremented and further data bytes may be transmitted by the master as necessary; one transmission may therefore contain a number of bytes of data to be wri tten to a sequential set of addresses (dummy bytes should be written to addresses not defined in the hdm8515 register set to continue this process). the process is terminated by the master generating a stop condition. figure 24 depicts this protocol. s slave address 0 a word address a p 7 bits 8 bits acknowledgement from slave r/w acknowledgement from slave acknowledgement from slave auto increment memory word address data byte a repeat if necessary s - start condition a - acknowledge p - stop condition f igure 24: i2c w rite to the hdm8515 5.4.2 i2c read from the hdm8515 to read information from the hdm8515, the master must first write the desired word address. hence the master must first generate a start condition and t ransmit the seven bit hdm8515 slave address defined on hi_data[6:0], with the eighth bit (read/not write) set to zero. once this has been acknowledged by the hdm8515, the master transmits the first word address from which it wishes to read information. t he master must then generate a second start condition and 47 retransmit the hdm8515 slave address, this time with the read/not write bit set to one (read). this will be acknowledged by the hdm8515, which then assumes the role of slave transmitter and transmi ts the requested byte. this byte should be acknowledged by the master receiver. if no stop condition is generated by the master, the hdm8515 will increment its word address pointer and transmit the next byte of information. this process is detailed in f igure 25. s slave address 0 a word address a s slave address 1 a data byte a 7 bits 8 bits 7 bits acknowledgement from slave r/w acknowledgement from slave acknowledgement from slave acknowledgement from master r/w auto increment memory word address data byte a p auto increment memory word address acknowledgement from master last byte s: start condition a: acknowledge p: stop condition hdm8515 becomes slave transmitter f igure 25: i2c r ead from the hdm8515 table 13: i2c slave address i2c_add0 i2c_add1 i2c_add2 i2c address 0 0 0 0000000 1 0 0 0000011 0 1 0 0001100 1 1 0 0001111 0 0 1 0110000 1 0 1 0110011 0 1 1 0111100 1 1 1 0111111 48 6. register definitions 6.1 write registers address (hex) 00, 01, 02 symbol timing frequency the 20 bit straight binary number in this field establishes the symbol timing frequency utilized within the demodulator. bit 7 of add ress 00 is the msb and bit 4 of address 02 is the lsb. if rs is the symbol rate and f c is the clock frequency, the value to be stored in this 20 bit field is the integer portion of r s (2 20 )/f c. 03 symbol timing loop gain control this field establishes t he k1 and k2 gain values for the second order loop filter of the symbol tracking loop. bits 0,1 ,2 and 3 determine the straight - through gain, and bits 4,5,6 and 7 determine the integration path gain. the nominal value of this parameter in hex, is expresse d below for different ranges of symbol rate to clock rate ratios: clock/ symbol rate value 2 fb 4 da 8 b9 16 98 32 77 64 56 04, 05, 06 carrier frequency the 20 bit, two's complement number in this field establishes the nominal carrier frequency of the demodulator. bit 7 of address 04 is the msb and bit 4 of address 06 is the lsb. the number in this 20 bit field multiplied by the clock frequency divided by 2 20 is the carrier frequency in hertz. when the carrier sweep function is active, this value defines the starting frequency. 49 07, 08 carrier loop f ilter control this field establishes the k1 and k2 gain values for the second order loop filter of the carrier tracking loop. bits 0,1,2 and 3 determine the straight - through gain, and bits 4,5,6 and 7 determine the integration path gain. the nominal value of this parameter in hex, is expressed below for different ranges of symbol rate to clock rate ratios. two loop filter configurations are provided at each symbol rate, one for steady state operation(08) and one which is used only for acquisition(07) to permit greater frequency pull - in. initially the gains are set to acquisition values. when qpsk_lock is achieved, they are automatically switched to steady state values. clock/ symbol rate steady state acqu. 2 c7 c7 4 a7 a7 8 87 87 16 67 67 32 47 47 64 27 27 09, 0a carrier sweep step size this 16 bit value defines the size of the step of each carrier frequency dwell. bit 7 of address 09 is the msb and bit 0 of address 0a is the lsb. the nu mber in this register is divided by 2 16 , and multiplied by the clock frequency to determine the frequency step increment. 0b, 0c symbols per dwell this 16 bit value defines the time, in symbol periods, for which the demodulator will dwell before making the next frequency step in a sweep. bit 7 of address 0b is the msb and bit 0 of address 0c is the lsb. 0d number of search frequencies this 8 bit field determines the number of frequency steps which occur during the frequency sweeping process. combine d with the frequency step size, this determines the frequency span of the carrier sweep. 0e narrow band agc initial value this 8 bit field establish es the initial gain of the narrow band agc. high numbers correspond to low gain associated with low sym bol rates. if the narrowband agc function is enabled, this number is used as a starting point and the closed loop will seek the optimum setting without processor interaction. 50 0f control parameters bit 0. binary/two?s complement when this bit is a zero, the system expects the six bit modulation input samples in two?s complement format, otherwise the input should be in offset binary format. bit 1. spectrum invert when this bit is set to zero, the spectrum of the received signal is inverted. thi s has the effect of complementing the in - phase channel only. bit 2. bias cancel enable when this bit is a one, the internal circuit which cancels dc bias on the i and q inputs is enabled. when this function is enabled, it is assumed that the input sig nal is scrambled with no significant dc component on either the i or q. bit 3. symbol track enable when this bit is set to one, the symbol tracking function is enabled. when this bit is zero the symbol tracking frequency is forced to the nominal 20 bi t programmed value. bit 4. carrier track enable when this bit is set to one, the carrier phase tracking function is enabled. when this bit is zero, the carrier frequency is forced to the 20 bit programmed value. bit 5. sweep hold when this bit is set to one, the sweeping process is inhibited, and the nominal carrier frequency remains at the last value. bit 6. narrowband agc mode 1 enable when this bit is set to one and the narrowband agc is in mode 1, the narrowband agc self - adjusts to the opti mum gain setting. when the bit is set to zero, the most recent value is held without updating. bit 7. automatic detection of spectrum inversion when this bit is set to one, the spectrum inversion is detected automatically. 51 10 reset functions bit 0. symbol timing frequency accumulator when this bit is set to zero, the frequency accumulator in the symbol tracking loop is cleared to zero. this bit must be set to one in normal tracking operation to implement a second order tracking loop, other wise the loop is first order. bit 1. carrier phase tracking frequency accumulator when this bit is set to zero, the frequency accumulator in the carrier phase tracking loop is cleared to zero. this bit must be set to one in tracking operation to implem ent a second order loop filter otherwise the loop is first order. bit 2. wideband agc accumulator when this bit is set to zero, the accumulator in the wideband agc is cleared to zero. in normal operation, this bit is set to one. when the wideband agc is set to mode 1, this bit has no effect as the integrator must be implemented in the external analog circuits. bit 3. narrowband agc accumulator when this bit is set to zero, the accumulator in the narrowband agc is cleared to the initial value define d in location 0e. in normal operation, this bit is set to one. bit 4. unused bit 5. carrier sweep function when this bit is set to zero, the sweep function is disabled and the carrier frequency is forced to the preset value defined in register locati ons 04, 05 and 06. bit 6. viterbi reset when this bit is set to zero, the accumulator for the signal quality is cleared to zero. in normal operation, this bit is set to one. bit 7. reed solomon error counter when this bit is set to zero, the counters for the number of corrected errors and the number of uncorrected code words are cleared to zero. 52 11 wideband agc control bit 0. wideband agc mode when this bit is set to one (mode 0), the wb agc output must be filtered with an external integrating a nalog filter to implement a first order feedback loop. when this bit is zero (mode 1), a digital integrator within the hdm8515 performs this function and the only external analog function required is a low pass filter to remove the high frequency componen ts of the sigma delta converter output. bit 1. wb agc invert when this bit is set to zero a high duty factor on the wb agc output corresponds to too much gain. when the control bit is set to one, high duty factor corresponds to not enough gain. bit 2. wb agc hold during normal tracking operation, this bit is set to one. when this bit is set to zero and the wideband agc is in mode 1, the digital integrator is held to the most recent value and loop updates are inhibited. bit 3. lnb hold when th is bit is set to one, the output of lnb - tone is held on zero. bit 4. i2c by - pass when this bit is set to zero, scl_i2co and sda_i2co are disabled. the default is one and data/clock can be by - passed. bits [7:5]. wb agc gain this three bit field def ines the time constant of the wb agc in mode 1. a value of zero corresponds to the shortest time constant and 7 corresponds to the slowest time constant. 12 lnb tone this eight bit value establishes the control for lnb tone generator. if f l is the d esired frequency and f c is the clock frequency, the value to be stored in this 8 bit field is the integer portion of f l (2 17 )/f c . the default value(20h) generates 22khz tone at 90mhz sampling clock. 13 sigma delta this eight bit input value establishes the control for sigma delta converter. this function is independent of other demodulator functions and is provided as control for external analog components. 53 14 test set - up the eight bit data written to this location defines the data presented on the 16 bit test bus. for configurations where the data is updated once per symbol period, the data changes at the rising edge of symbol_clock (in the case that symbol_clock remains high for consecutive clock cycles, the test port data will also change accordi ngly during the high period of symbol_clock due to the arrival of another symbol). bits [2:0]. test port configuration 00h output is tristate. 01h test bits [13:8] provide the i baseband filter output. test bits [5:0] provide the q baseband filter ou tput. this information is updated once per symbol period. 02h test bits [15:0] provide the sixteen most significant bits of the demodulator carrier phase test bits. this information is updated once per symbol period. 03h test bits [15:0] provide the s ixteen most significant bits of the demodulator symbol phase test bits. this information is updated once per symbol period. 04h test bits [15:8] provide the reed solomon output data. test bits [7:0] provide the deinterleaver output data. this information is updated at the reed solomon clock rate; when the transport stream output is configured to parallel output mode, data_clk may be used as an output clock for this data. 05h all zero. 06h test bits [13:8] provide the six bit i - channel data from the ad c. test bits [5:0] provides the six bit q - channel data from the adc. this information is updated at the fixed rate sample clock. 07h in this mode the test pins are used as input pins. the internal adc is disabled, and the inputs at the test pins are fe d directly to the demodulator. test bits [13:8] are used as i - channel input and test bits [5:0] are used as q - channel input. this information is updated at the fixed rate sample clock. bit 3. transport error indicator enable/disable enables/disables the transport error indicator,1 bit indicator in transport header. when this bit is set to 1 and if transport error is internally detected the transport error indicator bit is set to 1. when zero this functionality is disabled. 54 bit 4. this bit should be fi xed to zero bit 5. regulated data clock enables/disables the data and data clock regulator. when this bit is set to 1, data output and data clock are regulated by fifo operation. when this bit is set to 0, internal data output and internal data clock are by - passed bit 6. this bit should be fixed to zero. bit 7. clock polarity this bit is used to select the data_clk polarity either for serial or parallel transport interface. if this bit is set to zero(default value) , the transport data and control s ignals are latched at the positive edge of data_clk. otherwise, the signals are latched at the negative edge of data_clk. 15 viterbi lock threshold register 15 to 17 contain control parameters for synchronization in viterbi decoder. ordinary users are recommended to use the default value. bit[7:4] defines the lock threshold for vb_nodesync. viterbi decoder decides that the correct code rate has been found. a large number means it takes longer to find the correct code rate in automatic detection mode . it should be greater than 7. the default value is 12. bit[3:0] defines the lock fail threshold. viterbi decoder rejects a code rate and moves on to the next code rate. a small number means viterbi decoder tries more data before it moves to the next co de rate. it should be less than 7. the default value is 2. 16 viterbi unlock threshold this number defines the threshold to maintain the viterbi lock state. a large number means it needs more bad data to get out of the viterbi lock state and re - sta rt searching the correct code rate. the default value is 1. 55 17 viterbi byte - sync control once the viterbi lock(vb_nodesync) is achieved, the viterbi decoder tries to find the byte - sync. this 8 - bit register is used to set ?unlock - threshold? for the byt e - sync. large number means it needs more bad - data to get out of the byte - sync state, i.e. less sensitive to noise. the default value is 1. 56 18 control parameters for viterbi and rs decoders bit 0. parallel or serial output controls the transport stre am output of the 8515 to serial or parallel mode. ?0? (default) means the 8515 mpeg output is parallel. ?1? means the 8515 mpeg output is serial. the lsb of the data bus(data[0] - pin 98) is used as the serial output pin. bit 1. mpeg2 data ?0? (defaul t) means the incoming data is mpeg2 decoded. in this mode a sync byte is expected every 188 bytes. ?1? means non - mpeg2 data. the viterbi decoder doesn?t check the existence of the sync byte. bit [4:2]. depuncturing rate it defines the depuncturing rat e of the viterbi decoder. when vb_autocode is disabled, the depuncturing rate is set to this value. 0 --- 1/2 1 --- 2/3 2 --- 3/4 3 --- 5/6 4 --- 7/8 5 --- 6/7 bit 5. viterbi auto decoding mode when this bit is set to 1, the viterbi decoder automati cally finds the correct code rate of the incoming signal. when this bit is set to 0, the code rate is set to the user - defined value at bit[4:2]. the default is 0. bit 6. dss mode when this bit is set to 0, this device operates as dvb mode. when this bit is set to 1, this device operates as dss mode. in that case, the roll - off factor of the nyquist filter is set to 0.2. the default is 0 (dvb). bit 7. bpsk mode when this bit is set to 0, the demodulator assumes the incoming data is qpsk - modulated. when this bit is set to 1, the demodulator assumes the incoming data is bpsk - modulated. 19 rate 1/2 threshold select this seven bit parameter defines the threshold used in the viterbi decoder node synchronization process. for rate 1/2, the nominal va lue is 30 (1eh). 57 1a rate 2/3 threshold select this seven bit parameter defines the threshold used in the node synchronization process. for rate 2/3, the nominal value is 30 (1eh). 1b rate 3/4 threshold select this seven bit parameter defines the threshold used in the node synchronization process. for rate 3/4, the nominal value is 40 (28h). 1c rate 5/6 threshold select this seven bit parameter defines the threshold used in the node synchronization process. for rate 5/6, the nominal value i s 60 (3ch). 1d rate 6/7 threshold select this seven bit parameter defines the threshold used in the node synchronization process. for rate 6/7, the nominal value is 60 (3ch). 1e rate 7/8 threshold select this seven bit parameter defines the threshold used in the node synchronization process. for rate 7/8, the nominal value is 60 (3ch). bit 7. this bit should be fixed to zero. 58 1f bit 7. this bit should be fixed to zero. 20 unused 21 wideband agc threshold bits [5:0]. wideband agc thr eshold it determines the threshold of wide band agc accumulator. this value controls the magnitude of adc input. bit 6. unused bit 7. wideband agc frequency down it regulates wide band agc frequency. when this bit is set to zero, system clock for wide band agc frequency is sampling clock. otherwise, system clock for wide band agc frequency become sixteen times of sampling clock frequency. 22 scaling factor bits [2:0]. scaling factor this value manages to scale the soft decision demodulator outputs to the proper levels for the 4 bit soft decision viterbi inputs . if an overflow is detected, the output is limited to maximum or minimum 6 bit values. the upper four bits of this result are passed to the viterbi decoder. 00h qpsk output 01h qpsk outpu t * 1.25 02h qpsk output * 1.5 03h qpsk output * 1.75 04h qpsk output * 2.00 05h qpsk output * 2.25 06h qpsk output * 2.5 07h qpsk output * 2.75 59 23 clock generation pll control parameter - 1 bits [1:0]. vco range control vector default value is 1. bits [3:2]. pre divisor in case of extended frequency mode, this value is used the calculation of output frequency. default value is 0. bit 4. digital part test mode when this bit is set to 1and bit 7 of this register is set to 1, the pll is by passed and the external clock signal is directly connected to the internal clock. when this bit is set to 0, the generated clock of the pll is connected to the internal clock. the default is 1. bit 5. vco power down mode when this bit is set to 1, vco power down and does not oscillate bit 6. pll power down mode except vco when this bit is set to 1, pll power down and digital circuits do not operate and charge pump is disabled. bit 7. pll by - pass if this bit is set to 0 and digital part test mode ( bit 4 of this register) is set to 0, then pll normal frequency mode is selected. else if this bit is set to 1 and digital part test mode is set to 0, then pll extended frequency mode is selected. 24 clock generation pll control parameter - 1 bits [1:0]. u nused bit 2. counter toggle test internal used only. the default is 0. bits [5:3]. loop filter mode selector the default is 5h. bits [7:6]. charge pump test mode internal used only. the default is 0. 25, 26 m divider ratio this 14 bit value defines a feedback divider with a divider ratio m. bit 5 of address 25 is the msb and bit 0 of address 26 is the lsb. the default value is 002bh 60 27 n divider ratio it defines a reference divider with a divider ratio n. the default value is 01h 28 charg e pump bias current control vector bits [3:0 ] . the default value is 1. 29 diseqc message frame byte it defines the format of frame in diseqc message 2a diseqc message address byte it defines the format of slave address in diseqc message 2b diseqc message command byte it defines the format of command in diseqc message . 2c, 2d, 2e, 2f, 30 diseqc message data byte(s) for some diseqc message, additional data is carried in one or more subsequent data byte(s). 31 diseqc mode control bit 0. diseqc by - pass when this bit is set to 1, the function of diseqc interface is disabled. when this bit is set to 0, diseqc interface is enabled, the default is 1. bits [3:1 ] diseqc mode it determines one of following diseqc modes. 0: 22khz off 1: 22khz on continuous 2: burst mode - on for 12.5ms = ? 0 ? 3: burst mode - modulated 1:2 for 12.5ms = ? 1 ? 4: modulated with bytes from diseqc instruction. 5 - 7: reserved bits [7:4 ] diseqc message length number of byte in diseqc instruction , to output on diseqc pin. 61 6.2 read registers address (hex) 00 narrowband agc accumulator the current value of the 8 bit agc accumulator may be read from this location. 01, 02, 03 symbol timing frequen cy accumulator the current value of the 24 bit frequency accumulator in the symbol timing loop filter may be read from these 3 locations. 04, 05, 06 phase tracking frequency accumulator the current value of the 24 bit frequency accumulator in the ca rrier phase loop filter may be read from these 3 locations. 07 qpsk lock status bit 0. qpsk lock flag when this bit is set to one, the qpsk demodulator is phase locked. 08 wide band agc accumulator this eight bit value represents the most signif icant bits of the accumulator in the first order wideband agc loop. this data only has meaning when the wideband agc is in mode 0. 09, 0a sweep frequency the 16 bit sweep accumulator is available at this location. bit 7 of address 09 is the msb and bit 0 of address 0a is the lsb. the receiver frequency is determined by adding the sweep frequency with the carrier frequency accumulator (read addresses 04, 05 and 06) and the nominal carrier start frequency (write addresses 04, 05 and 06). 0b in - phas e the six lsb bit output of the in - phase baseband filter is available at this location. this data is updated once per symbol. 62 0c quadrature the six lsb bit output of the quadrature baseband filter is available at this location. this data is updated on ce per symbol. 0d noise power this eight bit output provides a measure of the noise component of the signal when qpsk lock is achieved. higher numbers correspond to lower signal - to - noise ratio conditions. the quality of this metric is improved if th e narrowband agc is disabled for a minimum of 1000 symbol periods before this parameter is read. 0e, 0f ber calculator the current value of the 16bit ber is used to monitor the signal quality or estimate the snr of incoming signal at the output of vit erbi. bit 7 of address 0e is the msb and bit 0 of address 0f is the lsb. it represents the number of errors among 2 20 data bits. 10, 11, 12 carrier frequency_1 this 24 bit value represents the carrier frequency of the first frequency translator. 13, 1 4, 15 carrier frequency_2 this 20 bit value represents the carrier frequency of second frequency translator. bit 7 of address 13 is the msb and bit 4 of address 15 is the lsb. 16,17,18 signal quality this 24 bit signal provides a measure of quality of the signal processed by the viterbi decoder. this parameter can be used to infer bit error rate and input signal - to - noise ratio for signals which are within a few db of threshold. bit 7 of address 16 is the msb and bit 0 of address 18 is the lsb. the spec ific definition of this signal for each coding rate is tbd. 19 viterbi rate this three bit number represents the code rate of the viterbi decoder. rate 1/2 0 rate 2/3 1 rate 3/4 2 rate 5/6 3 rate 7/8 4 63 1a reed solomon errors the four bit number at this location indicates the number of errors corrected in the most current block of 188 bytes. this number may range from 0 to 8. 64 1b fec lock bit 0. viterbi node sync when this bit is set to one, the viterbi decode r has successfully established node synchronization. bit 1. frame sync when this bit is set to one, the fec chip has successfully established word sync and frame sync. bit 2. viterbi byte sync when this bit is set to one, the viterbi decoder has successfully established byte - synchronization. bit 3. pi ambiguity when this bit is set to one, the viterbi decoder has successfully resolved pi ambiguity in the input data. (i.e inverted data) bit 4. pi/2 ambiguity when this bit is set to one, th e viterbi decoder has successfully resolved pi/2 ambiguity in the input data 1c,1d accumulated reed solomon errors these two registers present a count of corrected errors since it was last reset. bit 7 of address 1c is the msb and bit 0 of address 1d i s the lsb. these registers are reset by writing value to address 10 h . 1e accumulated reed solomon data this register presents a count of the uncorrected code words since it was last reset. when it reaches its maximum count(255), it rolls back to zero and starts counting again. this register is reset by writing value to address 10 h . 1f device identifier this register present device identifier. the current value of this register is f0h 23 reference divider test output internal used only. 24, 25 fe edback divider test output internal used only. 65 26 pll lock indicator bit 0. this 1 bit value represents the staus of pll lock if pll is locked, this value is 1, else 0. 66 appendix 67 a1. loop filter programming application note to illustrate that the symbol timing recovery loop and the carrier phase recovery loop are both programmable, several simulations were performed with different loop parameter co nditions. these simulations were performed with a symbol rate of two samples per symbol, corresponding to 30m symbols - per - second if a 60mhz clock were utilized. figure a1 illustrates the transient response of the symbol phase with three different loop conditions (k1=5, k2=10; k1=4, k2=9; and k1=8, k2=7). the vertical scale represents phase over a 360 degree range (524,287 to - 524,288). all test cases were run at high signal - to - noise ratio. the highest gain condition could be used for fast acquisitio n as well as for steady state with high code rate conditions, while the intermediate gain is a suitable steady state setting for rate 1/2 codes (minimum e b /n 0 of 4 db). the lowest gain setting corresponds to ultra low loop bandwidth and may be considered for maintaining lock without phase jumps during deep signal fades. f igure a1: s ymbol t iming r ecovery t ransient r esponse 68 figure a2 illustrates the transient response of the carrier tracking loop with the same loop bandwidth settings at high signal - to - noise ratio. the phase step for this test corresponds to 45 degrees. the actual bandwidth of the carrier loop is greater than that of the symbol loop for the same settings because the carrier loop must cope with greater dynamic s (such as frequency offset and drift). figure a3 illustrates the transient response of the carrier phase tracking loop under the same conditions at minimum signal - to - noise ratio (e b /n 0 of 4 db with rate 1/2 coding). the highest bandwidth case will pull in with a carrier frequency error of + or - .005 of the symbol rate at this minimum signal level. higher loop bandwidth may be programmed to provide greater pull - in with higher signal - to - noise ratio conditions. f igure a2: c arrier p hase r ecovery t ransient r esponse 69 f igure a3: c arrier p hase r ecovery t ransient r esponse with l ow snr 70 a2. false lock escape application note a qpsk signal will have inherent false lock states at frequency offsets of + or - n/4 of the symbol rate. mos t dbs signals which have symbol rates of 20m symbols - per - second or higher will not experience false lock because the carrier frequency uncertainty is less than 1/4 of the symbol rate. the hdm8515 is designed to process low data rate signals which may ex perience false lock, particularly at high signal - to - noise ratio conditions. the hdm8515 will permit recovery from false lock with some added host processor interaction. specifically, the processor must initialize the internal carrier frequency search har dware to search over a carrier frequency range of 1/4 of the symbol rate. if qpsk lock is achieved, but no viterbi lock is achieved, the processor would assume this is a false carrier lock, then program the hdm8515 to search another carrier frequency rang e covering 1/4 of the symbol rate. when both qpsk lock and viterbi lock have been achieved, the search is completed. this technique is reliable because the hdm8515 utilizes a fixed frequency clock which is not subject to inaccuracy associated with analog vcos. this accuracy insures that the multiple search ranges are perfectly continuous with respect to each other with no overlap. 71 a3. performance with interference. in order to evaluate the filter employed within the hdm8515 wit h respect to attenuating out - of - band interference, a test was performed utilizing the cossap simulator. the desired signal, at zero frequency, was configured to utilize 16 samples - per - symbol (corresponding to 3.75mhz symbol rate if a 60mhz clock is employ ed). an interfering signal was added with the same characteristics, except that the amplitude was made to be 10db higher than that of the desired signal, the data pattern was different and the carrier frequency was offset from that of the desired signal. several offset frequencies were evaluated for this case. figure a4 illustrates the spectrum of the test condition when the offset frequency is 1.35 times the symbol rate. figure a5 illustrates the measured bit error rate for various conditions. the e rror rate on the i channel was measured separately from that of the q channel, and the horizontal axis is scaled in db for one component (i or q of the signal). for example, the point labeled 1db corresponds to snr (noise bandwidth = symbol rate) of 4db o r e b /n 0 of 4db if rate 1/2 coding is employed. the theoretical performance for coherent psk is shown with the solid line. the curve closest to theoretical is the demodulator performance with no other interferers and corresponds to an implementation loss of about 0.2db. when the interferer was placed at a frequency of either 2.0 or 1.35 times the symbol rate away from the desired carrier, there is an additional degradation ranging from 0db to 0.1db. the worst case occurs when the interferer is placed at only 1.28 times the symbol rate from the carrier of the desired signal. in this case, the performance has degraded with respect to the no interference case by 0.3 to 0.5db. figure a6 illustrates performance with an interferer which is 20db higher than the desired signal and separated in frequency by 2 times the symbol rate. in this case, the performance has degraded by 0.7 to 0.8db from the case with no interferer. 72 f igure a4: a djacent c hannel i nterference of 10 d b, 1.35 s pacing 73 f igure a5 : p erformance with int erferer at different carrier spacings 74 f igure a6: p erformance with +10 d b i nterferer 75 a4. nyquist criteria considerations the hdm8515 is clocked at 60mhz, yet processes signals with s ymbol rates as high as 45m symbols - per - second. at first thought, this might appear to be violating the nyquist criteria which states that the sampling rate must be at least twice the highest frequency component. the total bandwidth of the 45msps signal, with 35% excess bandwidth, is about 60mhz. the samples provided to the hdm8515 are complex samples, which is equivalent to 120m samples - per - second, which does satisfy the nyquist criteria. another way of looking at this is to examine the baseband signa l. the signal bandwidth covers 60mhz, but the baseband spectrum covers from - 30mhz to +30mhz. there are no baseband frequency components greater than 30mhz, and the 60mhz clock is adequate as long as complex samples are taken. |
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